Design and support FPGA/SoC gateware solutions for power converter controls, leading a team of graduates.
At CERN, the European Organization for Nuclear Research, physicists and engineers are probing the fundamental structure of the universe. Using the world's largest and most complex scientific instruments, they study the basic constituents of matter - fundamental particles that are made to collide together at close to the speed of light. The process gives physicists clues about how particles interact, and provides insights into the fundamental laws of nature. Find out more on http://home.cern.
Are you a passionate and creative gateware engineer with experience in gateware DevOps? Join our team and work alongside experts in programmable technologies like FPGAs and system-on-chip (SoC) platforms. You will contribute to the design and support of both current and next-generation power converter controls, playing a direct role in our mission to deliver beam to our users.
You will join the Accelerator Systems Department (SY), which is responsible for the beam-related technical systems of the CERN accelerators. The SY teams design, build and operate equipment systems in all CERN accelerators, and are engaged in ambitious forward-looking R&D programmes.
The Electrical Power Converter Group (EPC) in the Accelerator Systems Department (SY) is responsible for the electrical power systems for the entire CERN accelerator complex. The Converter Controls Section (SY-EPC-CCE) is responsible for all of CERN's electronic power converter controls platforms; with existing systems using FPGA and future systems under development based on SoC. Our section is looking for a lead FPGA / SoC engineer, to take over the design and realisation of gateware solutions for these platforms, leading a team of graduates.
As FPGA / SoC Gateware Engineer, you will work in collaboration with users to create gateware solutions and manage the existing platforms, used in power converter controls. This covers the spectrum from gathering user requirements to providing user solutions, accompanied by test suites for long-term support.
Specifically, your functions will be:
Master's degree or PhD or equivalent relevant experience in the field of electronic engineering or computer engineering or embedded systems or a related field.
With a focus on FPGA design, SoC architecture, digital hardware design, or embedded systems development.
Spoken and written English or French, with a commitment to learn the other language.
Diversity has been an integral part of CERN's mission since its foundation and is an established value of the Organization. Employing a diverse workforce is central to our success. We welcome applications from all Member States and Associate Member States.
This vacancy will be filled as soon as possible, and applications should normally reach us no later than June 22, 2025 at 23:59 CET.
Contract type: Limited duration contract (5 years). Subject to certain conditions, holders of limited-duration contracts may apply for an indefinite position.
Working Hours: 40 hours per week
This position involves:
Participation in a regular stand-by duty, including nights, Sundays and official holidays.
Proven experience in SoC / FPGA technology, gateware DevOps, and initial team supervision experience.
Master's degree or PhD or equivalent relevant experience in electronic engineering, computer engineering, embedded systems or related field, with focus on FPGA design, SoC architecture, digital hardware design, or embedded systems development.